State of the art non-volatile memory devices are typically constructed by fabricating a floating-gate transistor in a silicon substrate. The floating-gate transistor is capable of storing electrical charge either on a separate gate electrode, known as a floating-gate, or in a dielectric layer underlying a control gate electrode. Data is stored in a non-volatile memory device by changing the threshold voltage of the floating-gate transistor through the storage of electrical charge in the floating-gate. For example, in an n-channel EEPROM (electrically-erasable-programmable-read-only-memory) device, an accumulation of electrons in a floating-gate electrode creates a high threshold voltage in the floating-gate transistor. When the control gate is grounded, current will not flow through the floating-gate transistor, which is defined as a logic 0 state. Conversely, a reduction in the negative charge in the floating-gate electrode creates a low threshold voltage. In this condition, with the control gate grounded, current will flow through the floating-gate transistor, which is defined as a logic 1 state.
For example, one particular type of non-volatile memory device is the flash EEPROM. Flash EEPROMs are a type of device that provide electrical erasing capability. The term "flash" refers to the ability to erase the memory cells simultaneously with electrical pulses. In an erase state, the threshold voltage of the floating-gate transistor is low, and electrical current can flow through the transistor, indicating a logic 0 state.
In a flash EEPROM device, electrons are transferred to the floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon gate electrode overlying the floating-gate electrode, and separated therefrom by a dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region of the floating-gate transistor. These applied potentials transfer electrons from the substrate through the tunnel oxide layer and to the floating-gate electrode. Conversely, the EEPROM device is erased by grounding the control-gate electrode, and applying a high positive voltage to either the source or drain region of the floating-gate transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and enter either source or drain regions in the semiconductor substrate.
Another type of EEPROM device is extensively used in programmable logic devices (PLDs). EEPROM cells formed in PLDs include three transistors: a write transistor, a read transistor, and a sense transistor. In conventional EEPROM cells, the control gates of the write transistor and read transistor are connected to the same wordline. Also, in PLD EEPROM cells, the read transistor and the sense transistor are connected to the same bitline. When the read transistor is turned on, the common bitline connection permits the sense transistor to be effectively used as the storage cell of the EEPROM.
In operation, to program PLD EEPROMs, a high voltage (between 13 and 15 volts) is applied to the wordline of the EEPROM cell. A relatively high voltage (approximately 11 to 12 volts) is applied to the control gate of the write transistor, allowing voltage applied on the bitline to be transferred to the control gate of the sense transistor. The application of such high voltage levels is a write condition that results in data being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage V.sub.cc is applied to the wordline of the write transistor, which also causes the read transistor to turn on. Ground potential is applied to the bitline, which is connected to the drain of the read transistor. A high voltage (between 13 to 15 volts) is applied on the capacitor coupled control gate (ACG). Under this bias condition, the high voltage applied to ACG is coupled to the floating-gate of the sense transistor and the EEPROM cell is erased by the transfer of electrons through the tunnel oxide layer from the floating-gate to the substrate.
Over time, both types of EEPROM devices will be written and erased repeatedly as data is stored and removed from the device. Since the EEPROM relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide layer underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide layer can cause charge trapping sites to form within the tunnel oxide. The formation of these charge trapping sites is undesirable, because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode, a data error occurs in the EEPROM device. In addition to causing charge to leak from the floating-gate electrode, the accumulation of charge in the trapping sites causes the threshold voltage of the floating-gate transistor to shift away from the originally designed threshold voltage. In an n-channel device, the accumulation of charge in the trapping sites causes the threshold voltage to shift to more negative values. Once the threshold voltage shifts away from the designed value, the floating-gate transistor cannot be turned on by application of a typical read voltage applied to the floating-gate electrode. When this happens, a read error occurs and an incorrect logic signal is transmitted from the EEPROM memory cell.
Both charge leakage and threshold voltage instability produce data errors during operation of the EEPROM device. Depending upon the particular function performed by the EEPROM device, the data error can cause catastrophic failure in an electronic system relying upon the EEPROM device. Accordingly, an improved EEPROM device and operating method is necessary to provide a high-reliability EEPROM device that exhibits stable threshold voltage values.